1. Field of the Invention
The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device that has a test circuit that generates a test signal that performs operational adjustment of internal circuitry.
Priority is claimed on Japanese Patent Application No. 2010-280571, filed Dec. 16, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
With the shrinking of semiconductor elements, manufacturing variations in process dimensions have come to greatly affect the electrical characteristics of semiconductor elements, and the operational characteristics of a semiconductor device have come to be easily influenced by manufacturing variations. For this reason, there is an increased need to use a test circuit provided within a semiconductor device to generate a test signal so as to perform an operational test of internal circuitry included in the semiconductor device. Given this, in order to have a test circuit generate a test signal to perform a test of the operating margin of internal circuitry, the internal power supply voltage and the internal signal timing are varied so as to cause malfunctioning of the semiconductor device to surface, and to detect the semiconductor device as a malfunctioning product having a small operating margin.
Japanese Patent Application Publication No. JPA 2001-243796 discloses a semiconductor device having a test circuit that generates a plurality of test signals.